The present invention relates to an architecture for a voltage controlled oscillator (VCO) circuit. More specifically, the present invention relates to a VCO circuit having an output with a reduced amount of jitter. VCO circuits are commonly implemented in phase-locked loop (PLL) circuits.
FIG. 1 is a block diagram of a conventional phase-locked loop (PLL) circuit 100. PLL circuit 100 includes voltage controlled oscillator (VCO) 101, phase comparator 102, loop filter 103 and divider circuit 104. VCO 101 generates an output clock signal, VCOOUT, in response to a frequency control feedback voltage (PLLFB) provided by loop filter 103. VCO 101 is an analog device, which is designed to generate a VCOOUT signal having a frequency that is controllable within a range about a desired frequency. The VCOOUT signal is provided to phase comparator 102 through divider 104. In the present description, divider 104 provides a divide-by-one function, such that the VCOOUT signal is provided to phase comparator 102. Phase comparator 102 is also coupled to receive a reference clock signal CLKREF. Phase comparator 102 determines the phase difference between the VCOOUT and CLKREF signals, and in response, generates an ERROR signal, which is representative of this phase difference. Phase comparator 102 includes phase/frequency detector 111 and charge pump 112, which are well-known, conventional elements.
Loop filter 103 integrates the ERROR signal, thereby creating the frequency control feedback voltage PLLFB. The frequency control voltage PLLFB, in turn, controls the frequency of the VCOOUT signal generated by VCO 101.
If the VCOOUT signal lags in phase with respect to the CLKREF signal, then phase comparator 102 generates an ERROR signal having a first logic level (e.g., Vcc). Loop filter 103 integrates this ERROR signal to create the frequency control voltage. This frequency control voltage, when applied to VCO 101, causes the frequency of the VCOOUT signal to increase, thereby causing the VCOOUT signal to gain in phase with respect to the CLKREF signal.
Similarly, if the VCOOUT signal leads in phase with respect to the CLKREF signal, then phase comparator 102 generates an ERROR signal having a second logic level (e.g., VSS). Loop filter 103 integrates this ERROR signal to create the frequency control voltage. This frequency control voltage, when applied to VCO 101, causes the frequency of the VCOOUT signal to decrease, thereby causing the CLKREF signal to gain in phase with respect to the VCOOUT signal.
In the foregoing manner, PLL circuit 100 continuously adjusts the frequency of the VCOOUT signal to eliminate any phase difference between the CLKREF and VCOOUT signals. The operating parameters of VCO 101, phase comparator 102 and loop filter 103 are selected to provide a stable closed loop control system. As a result, PLL circuit 100 ultimately eliminates the phase difference between the VCOOUT and CLKREF signals. At this time, the VCOOUT and CLKREF signals will be matched in both frequency and phase (i.e., synchronized). Under these conditions, PLL circuit 100 is said to be xe2x80x9clockedxe2x80x9d. PLL circuit 100 remains locked by continual small adjustments of VCO 101 based on the feedback received from phase comparator 102 and loop filter 103.
One of the most important characteristics of PLL circuit 100 is the jitter that is produced or transferred to the output signal (VCOOUT) of PLL circuit 100. The PLL loop bandwidth is the main characteristic that determines the amount of jitter at the output of PLL circuit 100.
FIG. 2 is a graph that illustrates the PLL loop bandwidth of PLL circuit 100. More specifically, FIG. 2 illustrates that PLL circuit 100 acts as a low-pass filter with respect to reference clock noise ("PHgr"n REF), and a high-pass filter with respect to VCO noise ("PHgr"n VCO). These sources are the main) contributors to PLL jitter. In order to reduce the noise from the reference clock, the PLL loop bandwidth should be decreased as much as possible. In order to reduce the noise from VCO 101, the PLL loop bandwidth should be increased as much as possible. However, these two requirements are in conflict with each other. As a result, a significant amount of jitter results from the VCO noise ("PHgr"n VCO) and the reference clock noise ("PHgr"n REF).
It would therefore be desirable to have a method and structure for reducing the amount of jitter present in the output signal of a PLL circuit.
Accordingly, the present invention provides a PLL circuit that includes a phase controller coupled to a voltage-controlled oscillator (VCO) in a feedback configuration. The phase controller significantly reduces the VCO phase noise ("PHgr"n VCO). As a result, a circuit using the VCO (e.g., a PLL circuit) will provide an output signal that exhibits reduced jitter. In one embodiment, the phase controller is coupled to receive the output clock of the VCO. In response, the phase controller generates phase measurement signals having voltages representative of the actual period of the output clock. These phase measurement signals are used to generate a control voltage, which is representative of both the actual period of the output clock, and the cycle-to-cycle deviation of successive periods of the output clock. The control voltage is applied to the VCO. The VCO adjusts the actual period of the output clock toward a desired period in response to the control voltage. The architecture of the present invention improves the jitter performance of a PLL circuit by at least a factor of five.